Digital-to-analog converters mainly designed for video applications have a very poor spectral purity when used in communication applications such as the transmit portion of wired and/or wireless digital communication systems. Delay differences between when a bit turns on and when it turns off results in a shift from the ideal fifty percent duty cycle (square wave) and leads to even-order harmonics in the output spectrum. For a given delay difference or skew in time (when a bit turns off or on), the higher the output frequency, the more pronounced the distortion. A typical prior art CMOS current-mode DAC switching scheme, shown in FIG. 1A, includes transistors 20 and 22; current source 24; input nodes Q and QB; and output nodes 26 and 28. In the circuit of FIG. 1, the time skew between Q and QB is of major concern for communication applications. The switches (transistors) 20 and 22 are like a differential pair. The prior art circuit of FIG. 1 uses PMOS transistors, but the same problems with time skew also exist when NMOS switches and current sources are used.
Individual current sources in current mode digital-to-analog converters (DACs) use differential switches to steer current through either one of the two switches. The above mentioned differential switches are controlled by two digital complementary control signals, Q and QB, where, if Q=VDD (power of the highest potential), then QB=VSS (ground or the lowest potential) and vice-versa. Due to the physics of the inverting circuit, there is always some time delay or skew between the original signal and its inverted counterpart. Normally, QB is derived by inverting Q, as shown in FIG. 1B, and thus, there is always some skew present between Q and QB. When current mode DACs are used in frequency domain applications, such as communications systems, the skew between, Q and QB introduces both harmonic and non-harmonic related distortion in the spectrum of the output signal. Hence, the spurious-free dynamic range (SFDR) of the DAC is greatly reduced.
Some attempts have been made in the prior art to improve the time skew problems described above. One example is U.S. Pat. No. 5,689,257 "Skewless Differential Switch and DAC Employing the Same", Nov. 18, 1997. In this patent, two cross-coupled inverters 29 and 30, as shown in FIG. 1C, are used to minimize the skew. However, this technique is limited by mismatches between the two inverters.